\subsection{Interrupt Injection}\label{subsec:int-injection}
The Muen kernel uses the Intel VT-x technology to provide a flexible interrupt
injection mechanism. Interrupt injection is needed to inform a subject about an
external interrupt or an inter-subject event.

The kernel provides a per-subject array of size 32 to store pending interrupts
for delivery.  Interrupts can only be delivered to a subject if it is ready to
receive interrupts (i.e. the subject is in an "interruptible" state). This can
be determined by checking the corresponding VMCS field (see Intel SDM
\cite{IntelSDM}, volume 3C, section 24.4.2). Furthermore the subject must have
the IF bit in the FLAGS register set. If these two conditions are true,
interrupts are injected by writing to the subject's VMCS interrupt information
field.

On the next VM entry, the virtual CPU (VCPU\index{VCPU}) executing subject code
is interrupted. The handling of an injected interrupt is analogous to the
handling of interrupts on a physical CPU and must be performed by the subject
(see \cite{IntelSDM}, volume 3A, chapter 6 for details on interrupt and
exception handling). Native subjects written in Ada/SPARK may use the minimal
interrupt handling packages provided by the Muen project, while VM subjects
continue to use their unmodified interrupt handling code.

To improve interrupt delivery speed and to decrease subject interrupt response
latency, the VMX "interrupt window exiting" feature is enabled in the subject's
VMCS if multiple events are pending or if an event can not be delivered because
the subject is not in an interruptible state. The feature causes a VM exit as
soon as the subject is ready to process interrupts again, causing the immediate
injection of the next pending interrupt.

If the per-subject pending interrupt array runs full, the kernel displays an
error message when running in debug mode. This state can happen if external
interrupts or events arrive faster than they are being delivered to a subject.

Upcoming Intel CPUs are expected to provide advanced
features\footnote{Posted-interrupt processing, APIC register emulation, Virtual
interrupt delivery} that may simplify the current interrupt injection mechanism
even further. Because these features are not widely available at the time of
writing, they are considered as future work and must be evaluated at a later
point in time, see section \ref{subsec:apicv}.
